1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a dynamically reconfigurable circuit configuration.
2. Description of the Related Art
A conventional semiconductor device such as an LSI is generally fabricated to be able to execute predetermined processing meeting required specifications, by determining, in a designing step, the arrangement of AND gates, OR gates, and the like and their interconnections so as to execute the predetermined processing. That is, to realize a desired function in a conventional semiconductor device, this semiconductor device realizing the function is fabricated by designing the circuit configuration (logic configuration) for each gate (on each gate level).
By contrast, a certain semiconductor device can change processing to be executed, even after its fabrication, by reconfiguring its circuit configuration. This reconfigurable semiconductor device has a plurality of arithmetic units capable of changing their functions, and can change processing to be executed by reconfiguring the circuit configuration in response to a control signal (configuration information) from a CPU.
In this conventional reconfigurable semiconductor device as described above, a plurality of memories (RAM1 to RAM3) 62-1 to 62-3 each having a predetermined memory capacity are arranged as shown in FIG. 5 to realize a desired function required by the user. In FIG. 5, reference numeral 61 denotes a bus (selector/register); and 63, an arithmetic unit. Although the arithmetic unit 63 is schematically illustrated as one arithmetic device, it is made up of a plurality of circuits (arithmetic devices or the like) in practice.
Unfortunately, although the conventional reconfigurable semiconductor device has the memories 62-1 to 62-3 as shown in FIG. 5, the memory size of each memory cannot be changed. Therefore, an inconvenience such as insufficiency of an address area occurs depending on the purpose (application). This sometimes extremely worsens the ease of use.
For example, even when the memories 62-1 to 62-3 shown in FIG. 5 each have the same memory capacity and the memories 62-1 and 62-2 have unused areas, these unused areas cannot be used as RAM3. Also, when, for example, the memories 62-1 to 62-3 are capable of inputting and outputting 64-bit data and the arithmetic unit 63 requires 128-bit data, this 128-bit data cannot be obtained at once. Therefore, 64-bit data is read out first, and then the remaining 64-bit data is read out by switching the memories.
If specifications are predetermined such as in normal board design, memories having optimum sizes are arranged in accordance with the specifications so as not to produce any unnecessary memory areas. However, the reconfigurable semiconductor device is so fabricated that the specifications can be changed even after fabrication. Since an application as an object is changeable, no optimum memory size can be determined. Accordingly, even when the reconfigurable semiconductor device has a large amount of memories, they are not effectively used in many cases.
In the fields of parallel processing using a plurality of conventional processors, a technique by which the processors optimize each local memory by reconfiguring the memory configuration by using switches and a technique by which the processors access an opponent buffer memory across a bus switch network are disclosed (e.g., Patent Documents 1 and 2).
[Patent Document 1]
Japanese Patent Application Laid-open No. Hei 1-94469
[Patent Document 2]
Japanese Patent Application Laid-open No. Hei 5-108586